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Altera_Forum's avatar
Altera_Forum
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14 years ago

PIO performance

Hi,

I use IORD and IOWR to control the PIO and it seems the speed will be no more than 15MHz. Is there any way to accelerate?

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Thanks akira. Could you give me details about how to use it in SOPC and control it in Nios? I read the document but it was not that clear.

  • Altera_Forum's avatar
    Altera_Forum
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    since I don't have much time to tell you.

    I just tell you a point.

    - SOPC builder has SG-DMA.

    - SG-DMA creates Avalon-ST data stream.

    - sample of DMA is in NiosII IDE template.

    it may take time to learn by yourself.

    but you need this skill if you need more than 100MB/sec.

    I'm sorry for now.
  • Altera_Forum's avatar
    Altera_Forum
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    Thanks again. I will try to understand it. Please leave me some detail/hint when you have time

  • Altera_Forum's avatar
    Altera_Forum
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    FYI it's not that the PIO is slow, the processor accessing the PIO can't access it every clock cycle. If you wired a DMA up to the PIO you could potentially change the output every clock cycle.

  • Altera_Forum's avatar
    Altera_Forum
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    Hi BadOmen,

    Could you explain more about the HDL driver? I read the document about these APIs. Do you mean that I need to give the base address of some PIO to sgdma?

    It will be perfect that you can show me a simply diagram of the whole connection.

    Thanks!
  • Altera_Forum's avatar
    Altera_Forum
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    It's pretty easy actually. With the DMA you basically read a buffer from memory and have the DMA write to a fixed address. The bit in the control field for writing to a fixed address is called "WCON" I think. There is something similar in the SGDMA but I forget what the bit is called. Take a look at this design, it does something similar: http://www.altera.com/support/examples/nios2/exm-crc-acceleration.html (http://www.altera.com/support/examples/nios2/exm-crc-acceleration.html?gsa_pos=1&wt.oss_r=1&wt.oss=crc)