PIO Interrupts PCIe

Hi again,

ah ok. The registers are always 32 bits wide. You have a problem with the comment "n-1" in the register map. In your case you only use the two least significant bits of each register. The 30 most significant bits are not used if you define only two inputs in sopc. But they are also present. The Address map will not change. If you take a look on the PIO Core pdf again you will find the line "Each PIO core can provide up to 32 I/O ports."

So if you define 32 Inputs in the SOPC, all bits of the register are used. Which of the 6 registers are necessary for you and must be handeled in software is depending on your settings. (i.e. "Enable bit-clearing for edge capture register")