PIO Interrupts PCIe

Hi JacoL,

thanks for your reply! Thanks for your PIO Core PDF, but i already looked into the "Embedded peripherals user guide" and thought i understand everything. I know that i must clear the bit by writing to them. My Problem is where is the register? Because my PIO have a width of 2 bit, but in documentation there stands 32bit?

"An Avalon-MM master peripheral, such as a CPU, controls and communicates with

the PIO core via the four 32-bit registers, shown in Table 9–2. The table assumes that

the PIO core's I/O ports are configured to a width of n bits."

So for example my PIO is on adress 0x4000.

interruptmask is on 0x4008

edgecapture is on 0x400C

In Table 9-2 in looks like the register only have the width of 2 in my example. I think that's my main understanding problem.

Thanks,

ringo

Ps: JacoL are you german?