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Altera_Forum
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13 years ago

PIO Core initialization value and pin output

I have a design which uses the Arria II GX and have used Qsys and Quartus v 11.1 SP2 to implement a design that, in part, utilizes a PIO component. I have initialized all the pins to outputs only an...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I'm not 100% but I think this behaviour is pretty normal.

PIO status is 'low' at reset and then it is controlled by an Avalon MM master (usually Nios), so it will not reach the required 'high' until the master has completed the reset sequence (in the Nios case, until it has reached the set-PIO-bits instruction)

I can't remember if Qsys lets you to specify a reset pio status. If not you can use one of these workarounds:

- if this is a bidir PIO, initialize it as 'all inputs', then set each pin function in software. after it has been assigned a known state

- tristate the fpga pins driven by PIO with a master_pio_enable signal, so you drive the opto isolators only when you are sure everything inside fpga has started