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Honored Contributorpciex4 ip core on cyclone iv gx F27
I have designed and data acquisition card. it uses pcie x4 interface to communacate with the host computer. the card is base on an cyclone iv gx 50 F672 fpga device, the quartus ii software ve...
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Honored Contributorpcie接口
Rx0-4、Tx0-4 REFCLK 使用Quartus 11.1的MegaWizard Plug-in Manager工具生成IP Compiler for Pcie Express V11.1。 在Quartus 11.1中对自动生成的工程进行编译，没有进行管脚绑定时，能够通过编译。 使用如下管脚绑定能够通过编译。 set_location_assignment PIN_T14 -to refclk set_location_assignment PIN_T15 -to "refclk(n)" set_location_assignment PIN_AA2 -to rx_in0 set_location_assignment PIN_W2 -to rx_in1 set_location_assignment PIN_U2 -to rx_in2 set_location_assignment PIN_R2 -to rx_in3 set_location_assignment PIN_Y4 -to tx_out0 set_location_assignment PIN_V4 -to tx_out1 set_location_assignment PIN_T4 -to tx_out2 set_location_assignment PIN_P4 -to tx_out3 使用如下管脚绑定不能够通过编译。 set_location_assignment PIN_T9 -to refclk set_location_assignment PIN_U9 -to "refclk(n)" set_location_assignment PIN_AA2 -to rx_in0 set_location_assignment PIN_W2 -to rx_in1 set_location_assignment PIN_U2 -to rx_in2 set_location_assignment PIN_R2 -to rx_in3 set_location_assignment PIN_Y4 -to tx_out0 set_location_assignment PIN_V4 -to tx_out1 set_location_assignment PIN_T4 -to tx_out2 set_location_assignment PIN_P4 -to tx_out3 问题在于通过编译的管脚绑定使用了REFCLK2，PCIE差分参考时钟经GPLL_1、MPLL_5，再用于PCIE CORE，而未通过编译的管脚绑定使用了REFCLK0、REFCLK1，PCIE差分参考时钟没有经过GPLL_1。 而我们的设计恰好将PCIE差分参考时钟绑定到REFCLK0，造成逻辑加载后没有任何反应。 编译器报错如下： Error (176559): Can't place MPLL or GPLL PLL "ip_pciex4_example_chaining_pipen1b:core|ip_pciex4_plus:ep_plus|ip_pciex4:epmap|ip_pciex4_serdes:serdes|ip_pciex4_serdes_alt_c3gxb_7ue8:ip_pciex4_serdes_alt_c3gxb_7ue8_component|altpll:pll0|altpll_nn81:auto_generated|pll1" in PLL location PLL_5 because I/O cell "refclk" cannot be placed in I/O pin Pin_T9 (port type INCLK of the PLL)。 具体图见附件。
