Honored Contributor
Honored ContributorThanks for Socrates's reply.
my problem is below: compilation succeeds pin assignment: ...... set_location_assignment pin_t14 -to refclk set_location_assignment pin_t15 -to "refclk(n)" set_location_assignment PIN_AA2 -to rx_in0 set_location_assignment PIN_W2 -to rx_in1 set_location_assignment PIN_U2 -to rx_in2 set_location_assignment PIN_R2 -to rx_in3 set_location_assignment PIN_Y4 -to tx_out0 set_location_assignment PIN_V4 -to tx_out1 set_location_assignment PIN_T4 -to tx_out2 set_location_assignment PIN_P4 -to tx_out3 compilation failed pin assignment: set_location_assignment pin_t9 -to refclk set_location_assignment pin_u9 -to "refclk(n)" set_location_assignment PIN_AA2 -to rx_in0 set_location_assignment PIN_W2 -to rx_in1 set_location_assignment PIN_U2 -to rx_in2 set_location_assignment PIN_R2 -to rx_in3 set_location_assignment PIN_Y4 -to tx_out0 set_location_assignment PIN_V4 -to tx_out1 set_location_assignment PIN_T4 -to tx_out2 set_location_assignment PIN_P4 -to tx_out3 the error message: Info (167065): Input frequency of fixedclk for the GXB Central Control Unit "ip_pciex4_example_chaining_pipen1b:core|ip_pciex4_plus:ep_plus|ip_pciex4:epmap|ip_pciex4_serdes:serdes|ip_pciex4_serdes_alt_c3gxb_7ue8:ip_pciex4_serdes_alt_c3gxb_7ue8_component|cent_unit0" must be 125.0 MHz error (176559): can't place mpll or gpll pll "ip_pciex4_example_chaining_pipen1b:core|ip_pciex4_plus:ep_plus|ip_pciex4:epmap|ip_pciex4_serdes:serdes|ip_pciex4_serdes_alt_c3gxb_7ue8:ip_pciex4_serdes_alt_c3gxb_7ue8_component|altpll:pll0|altpll_nn81:auto_generated|pll1" in pll location pll_5 because i/o cell "refclk" cannot be placed in i/o pin pin_t9 (port type inclk of the pll) Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Error (171000): Can't fit design in device Warning (169177): 2 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV GX Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. Info (169178): Pin pcie_rstn uses I/O standard 3.3-V LVCMOS at U19 Info (169178): Pin local_rstn_ext uses I/O standard 3.3-V LVCMOS at W26 Error: Quartus II 32-bit Fitter was unsuccessful. 2 errors, 14 warnings Error: Peak virtual memory: 335 megabytes Error: Processing ended: Sun Jan 29 10:47:12 2012 Error: Elapsed time: 00:00:12 Error: Total CPU time (on all processors): 00:00:10 Error (293001): Quartus II Full Compilation was unsuccessful. 4 errors, 535 warnings but, my card select the failed pin assignment. please help fix the problem.
