PCIe w/ Avalon ST: Equivalent of ko_cpl_spc_vc0?

Brendan,

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I had hoped that the PCIe hard macro would provide me with the realtime status of the CPLH/CPLD buffers, so that I could have a cleaner implementation in hardware, and one with finer granularity. I had also hoped that I could find out from the PCIe hard macro when my algorithm failed, and CPLH/CPLD buffer overrun occured. This would be very useful during the debug process, but would also improve overall system reliability in that I could use this to throw an interrupt and alert the driver that something had gone wrong.

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I had hoped that, too. At first I was glad to see that, according to the PCIe compile manual, the IP would filter out (read) completions that don’t belong to read requests. I understand that the IP can track my read requests as they hit the PCIe network and can account for received completions. But in no way it can account for the operation of my Completion Timeout mechanism implemented solely inside the application. That means: In case of Completion Timeout I have to drop completions of which the IP block doesn’t know they have already timed out, until the tag is freshly used for the next read request. This means:All the tag handling logic currently in the IP for catching invalid completions is worthless and has to be duplicated in an application-specific way inside my logic.

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I can achieve all the functionality I need by doing all of the monitoring/allocating/freeing in my logic. I can use the timeout mechanism to find out when buffer overrun occurs. Its all doable, just more work on my end.

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Hmmm … I don’t quite understand what the timeout mechanism has to do with detecting buffer overruns. The timeout mechanism just ensures that the user logic doesn’t have to block and wait forever for a lost read request or completion but can continue, probably dropping data or requiring a soft reset of hardware, driver and/or user software. Just look at the description of cpl_err[] and the chapter about Error Handling to see what to do in which case. You cannot detect buffer overruns, and you should do your part of preventing overruns by properly handling CPLH/CPLD before sending a read request – the PCIe IP already does so for all other credit-based transactions.

And, yes, it’s all work on your end. ;)