PCIe w/ Avalon ST: Equivalent of ko_cpl_spc_vc0?

Thanks again, Matthias, for another very detailed explanation.

I had already implemented the LIMIT_FC algorithm, using a fairly crude mechanism to allocate and free the read request CPLH/CPLD buffers, and this has been working fine in actual hardware. As you mention in your reply, this really has to be associated with the tag allocation and freeing. I had hoped that the PCIe hard macro would provide me with the realtime status of the CPLH/CPLD buffers, so that I could have a cleaner implementation in hardware, and one with finer granularity. I had also hoped that I could find out from the PCIe hard macro when my algorithm failed, and CPLH/CPLD buffer overrun occured. This would be very useful during the debug process, but would also improve overall system reliability in that I could use this to throw an interrupt and alert the driver that something had gone wrong.

I can achieve all the functionality I need by doing all of the monitoring/allocating/freeing in my logic. I can use the timeout mechanism to find out when buffer overrun occurs. Its all doable, just more work on my end.

Thanks,

Brendan