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Altera_Forum
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16 years ago

PCIe w/ Avalon ST: Equivalent of ko_cpl_spc_vc0?

While the Avalon ST interface is a little bit easier to handle than the Descriptor/Data Interface, I do miss ko_cpl_spc_vc0, required for proper Rx buffer overflow prevention. The SGDMA example solve...
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Altera_Forum
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15 years ago

Hi Matthias

Did you ever find a solution to this problem? I have a similar situation where I am using the Avalon ST interface to the PCIe hard macro in an Arria II GX, and am running into rx buffer overflow. As far as I can tell, none of the test_out[63:0] signals let me see either the rx buffer overflow status, or rx buffer space available.

The only solution I have found is to limit the number of MRd requests issued so that there is space for them in the rx buffer, based on the PCIe Megawizard settings, and knowing the max payload size (256 or 128bytes) and host system read completion boundary size (64 bytes in my case.

Thanks

Brendan