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Altera_Forum
Honored Contributor
14 years agoPCIe Type and Bar
Hi pcie type 1. A platform that has a CPU(PCIe root complex embedded in it) connects to the FPGA via PCIe. Inside the FPGA, it has a nios ii processor, dma, memory controller, pheriph...
Altera_Forum
Honored Contributor
14 years agoI've just failed to find a note of the performance we got :-(
There were a lot of problems with the PCIe hardware layer and it doing resyncs all the time. I thought we'd got read and write below 1us. However using host DMA (and spinning waiting for the result) sped the code up significantly as the 'cost per byte' is minimal. I did have to write a driver for the 'ppc 83xx PCI Express CSB bridge' - in itself not for the faint-hearred!