PCIe Type and Bar

pcie type

1- The Root complex is only one in the system and can configure all the endpoints.

So the FPGA need only to be an end point.

In the example you give the bridge is not needed.

2- All application do not need the root complex if there is one in the system.

3- Cannot understand the question..

I suggest that you have a better look at PCIe system prior to your design.

pcie bar

1- You can know the BAR size once you need how much memory you want to view from this bar.

For example if at that bar you attach a 1MB Dual Port, a 1MB Fifo and 1MB of registers or something else (that can be seen as a sort of register map) the BAR Size need to be the sum of all these.

2- A Bar is a Base Address Register that is a sort of "chip select" moved by the Master of the communication (ie. Root Port) each time it has to access to a memory mapped into it.

Note that I speak about memory because the concept is that a under a BAR the Root port see a memory zone.