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Altera_Forum
Honored Contributor
Honored ContributorPCIe transceiver offset cancelation
Device - Stratix IV Using PCIe x4 Gen2. For the purpose of Transceiver offset cancelation I am using the external alt_gx_reconfig. I have been using a PLL output to feed this clock and using th...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Let me get back and do some more checking, I was thinking that the reset might be pulled up high at power-on and host asserts the reset once the BIOS chip is powered up and host starts its enumeration sequence. I will check more on the timing aspect of things and get back with more data, --- Quote End --- Its quite possible that is the case, and it would probably be acceptable. Its worth poking around in your hardware to get a sense of what is going on at the system level, and then write your testbenches to match that and several other power-up sequences to see if your design behaves correctly. Cheers, Dave
