Occasional Contributor
Frequent ContributorHello Sir,
For MSI-X, you will need to configure the parameters in the IP GUI as below:
IP Settings -> Interrupt capabilities -> PF0 (VF) MSI-X
And this parameters is map to the Figure 46 “MSI-X Capability Registers” as describe in the UG- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_sriov.pdf#page=82
So, from the host (driver), you will need read these MSI-X capabilities register to check the table and PBA offset.
Occasional ContributorHi !
Thanks for your reply. Could you please try to elaborate more ? I am not sure , I get the complete picture. Based on what I read, the table size is equivalent to how many vectors can be generated. If you set the VF msi-x table size to 2. Does this mean you have two distinct interrupts that can be generated ? Does this also mean that every other VF also has this msi-x table of size 2 as well ?
I also need more clarification on where the msi-x table and pba table actually reside. For example, if I set BIR to be 0 for VFs. Where does this table actually reside? Is it in the user-application on-chip memory of the VF bar0 at address offset 0 ? Then to generate an interrupt for VF 1 go to that memory location read the addresses and set the request and set the PBA to the appropriate value ?
Based on the documentation provided in the user guide. It seems to me that the user-application logic needs to know, where the MSI-X table is to read the address and data for a specific interrupt to trigger.
