Honored ContributorHello,
Has anyone noticed that Qsys does not generate the simulation testbench for PCIe? In SOPC builder, if the generate simulation model option is selected, it will automatically include the simulation model. Can this model be generated from Qsys, just as you could from SOPC Builder? And if so, how?
Honored ContributorOk,
So it looks like you MUST export the conduit signals (ref_clk, etc.) within Qsys, select the simulation model AND testbench options (selectable from within the generation tab), and then generate the system. This will provide the simulation environment, including all of the BFMs for the PCIe. Following this recommendation, you will have a system that looks similar to the equivalent SOPC system simulation testbench. Hope this helps someone!Honored ContributorBy the way, if you go Altera.com, PCIe and external memory example, you can find example design with simulation.
The Stratix4 GX example does have code to stimulate Qsys. https://www.altera.com/support/software/download/refdesigns/ip/interface/dnl-pciexpress-ddr3-sdram.jspHonored Contributorhey !!
Anybody tried to simulate the qsys design example (it´s an pci express system to an dma and onchip ram) mentioned in the "IP compiler for PCI Express User Guide" chapter 17 ? When i run the simulation in modelsim i always end up with a break and the following message: SUCCESS: BFM model not available somebody has got a solution to this problem ? I´m using quartus II v11.0 sp1... thanks for ur help guys !!Honored ContributorAfter Q11.0 sp1, the BFM was stopped shipping.
If you want to simulate, you need to stick with Q11.0Honored Contributorcrazy, just installed v11.0 sp1 cause EP2AGXE6XXFPGA isn´t available in v11.0, but then they stop supporting bfm´s :-(
anyway, thanks for ur help
