PCIe PIO Beginner Questions

Read this thread:

http://www.alteraforum.com/forum/showthread.php?t=35678

Download the PDF and zip file. You can port the design to your kit.

If you want to read/write from the FPGA via PCIe to talk to another PCIe device all you need to do is

a) Use the host PC to determine the PCIe address of the device you need to talk to.

b) Configure the Qsys PCIe address remap registers (the 1MB region discussed in the document) so that it maps to the region of the device you want to control.

c) Issue a read/write to the Avalon-MM slave interface of the Qsys PCIe component. That Avalon-MM transaction will map to a PCIe transaction that will then perform a read/write to the PCIe device.

And that's it. Simple, eh :)

Cheers,

Dave

Dave,

Thanks for the quick reply, and for your incredibly explicit directions in the pdf. I feel a bit like an idiot asking more of you but, I did get stuck in your directions very close to the end at the "Source Contraints" step. I found the .tcl file, but I'm not sure how to source it and I assume once I do that successfully the following line of code will work, but at the moment it does not for me. I also tried your autogeneration thing, but quartus 12.1 threw a bit of a fit. I would rather step through it instead of auto-generating though, so I'm more interested in what you meant about those constraints.

Some comments I noticed:

Everything I've seen always has a DMA block connected to the pcie block. Since my data transfers are relatively basic, I was wondering if that was really necessary (I've read DMA has a large overhead, and so is not efficent for small amounts of data).

From a curiosity standpoint, is there a way to configure this thing without having to use the host PC? Isn't there a way to find the PCIe addresses without just finding it on the host PC? I thought my idea of polling the physical addresses wasn't the worst thing...

And as a more general question, is the purpose of this whole thing to have something like a PCIe block that just has a more basic interface (tx/rx) kind of thing to be used in other designs?

Thanks so much for your help thus far,

Craig

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I feel a bit like an idiot asking more of you but ...

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Don't feel bad. The tools are complicated and the official documentation and examples often suck ...

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I did get stuck in your directions very close to the end at the "Source Contraints" step. I found the .tcl file, but I'm not sure how to source it

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The word 'source' is Tcl programming terminology.

In Quartus, you click the mouse in the Tcl console window (View->Utility Windows->Tcl console), and at the tcl prompt you type

tcl> source $TUTORIAL/hdl/s4gxdk/share/scripts/constraints.tcl

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I assume once I do that successfully the following line of code will work, but at the moment it does not for me.

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Let me know if it doesn't.

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I also tried your autogeneration thing, but quartus 12.1 threw a bit of a fit.

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If you have trouble sourcing the constraints file, I'll re-run the test on 12.1 and fix the problem.

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I would rather step through it instead of auto-generating though, so I'm more interested in what you meant about those constraints.

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Excellent attitude! :)

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Everything I've seen always has a DMA block connected to the pcie block. Since my data transfers are relatively basic, I was wondering if that was really necessary (I've read DMA has a large overhead, and so is not efficent for small amounts of data).

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It depends on what and when you consider programming the DMA controller 'overhead'.

The naive way to think of using a DMA controller is that you use the processor to write the DMA controller registers to setup the transfer, and then wait for the interrupt to indicate the DMA transfer is done. That is overhead.

The more typical way to use a DMA controller is that you use the processor to setup a scatter-gather buffer of "things to do", and then enable the DMA controller to do them completely independent of the CPU. The CPU may or may not have to service ISRs, depending on what your scatter-gather buffer is doing, eg., reading a temperature sensor and DMAing the result to a 7-segment display can be done completely independent of the CPU.

Anyway, that'll give you an idea of why a DMA controller might be useful.

With respect to PCIe transactions, the most efficient transactions are always implemented by a bus master issuing burst transactions. An x86 CPU or NIOS II CPU will not generate those sorts of transactions, so you use a DMA controller.

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From a curiosity standpoint, is there a way to configure this thing without having to use the host PC? Isn't there a way to find the PCIe addresses without just finding it on the host PC? I thought my idea of polling the physical addresses wasn't the worst thing...

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You need a PCIe end-point to configure the PCIe address map. The PCIe end-point is generally the source of the PCIe reference clock and in the old-days of PCI, it was where the interrupt lines routed and the bus arbiter lived. You can do this with an FPGA, but that is not how the development boards are wired.

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And as a more general question, is the purpose of this whole thing to have something like a PCIe block that just has a more basic interface (tx/rx) kind of thing to be used in other designs?

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Which "whole thing" are you talking about? The Qsys PCIe block? The purpose of that block is "a black box that can speak PCIe" :)

The alternative is implementing TLP packet parsing ... refer to the PCIe spec ...

Cheers,

Dave

Dave,

First off I want to thank you for your quick, exceedingly helpful responses, as well as your words of encouragement. I've been working on this trying to avoid asking another question (and skiing lake tahoe) but I think I have one last round of questions I still need to come through.

First off, about that thread you link in the beginning. The autocode generation did not work for me (12.1) but more importantly the step by step has not compiled either. The error its throwing is "pcie_pipe_ext_gxb_powerdown does not exist in macrofunction 'u5'(dbl clicking this reveals it is having problems with the top level .sv file)." The same error pops for ...pll_powerdown. I've been looking at this and it might be that my knowledge of system verilog is limited to the altera training, but I can't figure out what's up. the line ".pcie_pipe...powerdown (somevar)," definitely exists. If I look at the qsys_system.v file, pcie_pipe...powerdown is not assigned as an output. In fact the directions don't ask the powerdown signals on the pcie block to be exported. If you do export them it generates "pcie_powerdown_gxb_powerdown" and not what is in the .sv file. I tried renaming the .sv file to match the system.v file, tried deleting it all with and without exporting the powerdown group in qsys and I can't get the error to go away. Not sure where I've gone wrong, but I can't think of what else to try.

Second question is more about building understanding. So in your program there is the RAM, PCIe, and DMA block... so how does it ever know to do anything? Maybe it doesn't since you were just using it to test timing, in which case how do I get it to follow my directions? My current state of mind is that if I make a happy state machine as a .v, I can apparently turn that into a custom avalon mm block. Naive to what that entails, I could then hook it up in qsys to.. something. In your first post it sounds like I can hook it directly up to the PCIe block, but don't I have to go through the DMA guy? I thought the whole point of the DMA fella was to be able to interact with the PCIe block.

Thanks!

PS: thank you so much for correcting my impression of DMA. That was an "ooOOoo" moment over here

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First off, about that thread you link in the beginning. The autocode generation did not work for me (12.1) but more importantly the step by step has not compiled either.

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That is a frustrating reflection of Altera's tools. Most of the time Altera's examples will not even recompile!

Install the version I used to create the PCIe example designs, and start from there - at least then you have a working reference design.

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The error its throwing is "pcie_pipe_ext_gxb_powerdown does not exist in macrofunction 'u5'(dbl clicking this reveals it is having problems with the top level .sv file)." The same error pops for ...pll_powerdown. I've been looking at this and it might be that my knowledge of system verilog is limited to the altera training, but I can't figure out what's up. the line ".pcie_pipe...powerdown (somevar)," definitely exists. If I look at the qsys_system.v file, pcie_pipe...powerdown is not assigned as an output. In fact the directions don't ask the powerdown signals on the pcie block to be exported. If you do export them it generates "pcie_powerdown_gxb_powerdown" and not what is in the .sv file. I tried renaming the .sv file to match the system.v file, tried deleting it all with and without exporting the powerdown group in qsys and I can't get the error to go away. Not sure where I've gone wrong, but I can't think of what else to try.

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The altgx and altgx_reconfig components describe these signals in detail. Its possible that the PCIe IP now internally instantiates the required component. I'd have to re-read the PCIe handbook and look at the code, however, I don't have time to do that right now, sorry. Think of it as a good exercise in learning for yourself :)

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Second question is more about building understanding. So in your program there is the RAM, PCIe, and DMA block... so how does it ever know to do anything?

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The host PC can always write to registers on the board, so it can control "what to do".

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how do I get it to follow my directions? My current state of mind is that if I make a happy state machine as a .v, I can apparently turn that into a custom avalon mm block.

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You can create an Avalon-MM master to initiate "what to do", or you can instantiate a NIOS II core and have its software determine "what to do". You could even use your host PC to setup a DMA controller, and have the DMA controller perform a fixed sequence of tasks.

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I thought the whole point of the DMA fella was to be able to interact with the PCIe block.

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Nope, its just there to generate burst transactions.

Cheers,

Dave

PS. If you're driving back from Tahoe down 395, stop by and say hello :)

hi to all,

i have to implement dma read data found in memorymap and write that on PIo or peripphical.

do somebody have doing this exercice.

please i need your help.*

I've started the programme , but i think my problem came from on my c program