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First off, about that thread you link in the beginning. The autocode generation did not work for me (12.1) but more importantly the step by step has not compiled either.
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That is a frustrating reflection of Altera's tools. Most of the time Altera's examples will not even recompile!
Install the version I used to create the PCIe example designs, and start from there - at least then you have a working reference design.
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The error its throwing is "pcie_pipe_ext_gxb_powerdown does not exist in macrofunction 'u5'(dbl clicking this reveals it is having problems with the top level .sv file)." The same error pops for ...pll_powerdown. I've been looking at this and it might be that my knowledge of system verilog is limited to the altera training, but I can't figure out what's up. the line ".pcie_pipe...powerdown (somevar)," definitely exists. If I look at the qsys_system.v file, pcie_pipe...powerdown is not assigned as an output. In fact the directions don't ask the powerdown signals on the pcie block to be exported. If you do export them it generates "pcie_powerdown_gxb_powerdown" and not what is in the .sv file. I tried renaming the .sv file to match the system.v file, tried deleting it all with and without exporting the powerdown group in qsys and I can't get the error to go away. Not sure where I've gone wrong, but I can't think of what else to try.
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The altgx and altgx_reconfig components describe these signals in detail. Its possible that the PCIe IP now internally instantiates the required component. I'd have to re-read the PCIe handbook and look at the code, however, I don't have time to do that right now, sorry. Think of it as a good exercise in learning for yourself :)
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Second question is more about building understanding. So in your program there is the RAM, PCIe, and DMA block... so how does it ever know to do anything?
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The host PC can always write to registers on the board, so it can control "what to do".
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how do I get it to follow my directions? My current state of mind is that if I make a happy state machine as a .v, I can apparently turn that into a custom avalon mm block.
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You can create an Avalon-MM master to initiate "what to do", or you can instantiate a NIOS II core and have its software determine "what to do". You could even use your host PC to setup a DMA controller, and have the DMA controller perform a fixed sequence of tasks.
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I thought the whole point of the DMA fella was to be able to interact with the PCIe block.
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Nope, its just there to generate burst transactions.
Cheers,
Dave
PS. If you're driving back from Tahoe down 395, stop by and say hello :)
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