Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

pcie megawizard

I do not want the CHAINING DMA application, all I want is the core with the Avalon ST interface.

The megawizard generates the unwanted DMA app. !!

My app is based on the PCIE TLP layer, so I need to know in which hdl file I find the Avolon ST interface and the modules required to build the PCIE.

Which files do I not need for this ?

Thanks HB

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hello,

    When ever you have a PCIe IP in your qsys project, examples files are generated. You can switch of the Chaining DMA example by editing the driver bfm file. You can also do read and write operations by using the tasks given in the testbench section of the [IP compiler for PCIe express manual]

    Thanks,

    AA
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks for the responds.

    I do not have a QSYS design. I want to connect my app to the AVALON ST interface.

    I just need signals like rx_st_sop rx_eop rx_st_data(63 downto 0). same for tx,

    again, I would like to know the file where I find this signals, and want to know what files of the chaining dma I could delete.

    The signals are well described in IP Compiler for PCI Express User Guide, page 5-3, but which is the corresponding hdl file to connect to these signals

    the BFM is for simulation only, correct ??

    Thanks HB
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hello,

    I think you will have to manually map the signals in a new HDL file, in order to connect the PCIe signals [conduits] to your design.

    I haven't deleted any DMA files till now, I have just switched off the DMA test.

    Yes, the BFM's are for simulation only, you don't have to worry about these getting synthesized on your FPGA, because the HDL code for these BFM's will be switched off automatically.

    Thanks,

    AA