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Altera_Forum
Honored Contributor
Honored ContributorPCIe IP target->host MRd but no completion
Hello, I am using the PCIe IP (9.0). I recieve posted and non-posted TLPs from the host (PC) and send completion TLPs back and everything works great. However, when I initiate an MRd from...
Altera_ForumHonored Contributor
Honored ContributorI created a module to simulate the signals that the pcie core is supposed to be asserting when the completion comes back and everything works as it is supposed to. But, back to the real thing, I am suspecting the completion logic is being optimized -- specifically, the optimization report includes this highly suspicious line:
pcie_handler:u_pcie_handler|mypcie:u_pcie|mypcie_core:wrapper|altpcie_64b_x4_pipen1b:altpcie_64b_x4_pipen1b_inst|pciexp4x125_pipe:core_inst|pciexp64_trans:trans|pciexp64_rxtl:rxtl|mem_cpl Could this mean the memory completion logic is being optimized, and hence no rx_req? The reason it was optimized was "Stuck at GND due to stuck port data_in" Has anyone seen this before?
