PCIe IP target->host MRd but no completion

I opened a ticket with Altera. They want me to check my design and run it in a testbench. I think I will do that and see. It is weird though since everything else works. Even MRw TLPs from the target to the host work fine. What I am wondering is if the logic that is responsible for asserting the rx_req is different depending on whether the rx_desc from the host is a completion rather than a new TLP. If that is the case, then there could be a possibility that something is getting optimized out...