PCIE IP Core question

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I'm a new one in PCIE exploration,I have came up against some problems when reading the pcie compiler user guide handbook.If i use the pcie IP core and DMA controller IP core together in my design based on the SOPC builder（without the cpu core）, I think i should connect the DMA read mast port to the PCIE Tx slave port, thus when the DMA transmit a read request via the PCIE Tx slave port,a read completion will be recieved by the PCIE Rx master port.

My questions as follows are:

1 Which slave port should i connect to the PCIE Rx master port? I can't find the proper slave port,because the DMA has two master data port.

2 The PCIE Tx slave port has the read,readdata signals which is discribed in the handbook, but I can't find the opportunity to use these signals.

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No, when the DMA transmit a read request via the PCIEx Tx Slave, the data will be received via PCIEx Tx Slave. You don't have to receive and interpret the read completion. The core do this automatically and deliver the data request on avalon slave interface.

The read, readdata signals are connected internally on the SOPC System with the signals of the DMA Read Master of DMA Controller.

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No, when the DMA transmit a read request via the PCIEx Tx Slave, the data will be received via PCIEx Tx Slave. You don't have to receive and interpret the read completion. The core do this automatically and deliver the data request on avalon slave interface.

The read, readdata signals are connected internally on the SOPC System with the signals of the DMA Read Master of DMA Controller.

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Thanks a lot for your reply,which helps me very much! If your reply is correct, the discriptions in page 4-26 to 4-28 of the PCI Express Compiler User Guide version8.0 may be incorrect,at least not integrated.