PCIe Interrupts from Qsys/Arria II GX

Hello,

So their are 2 mechanisms im familiar with . The first is by using the Msi and the standard irq ports like nios has. The standard sound like the one you mentioned on the cra. But I usually don't write to the cra and let qsys handle the interrupt. The msi method can support more irqs since the standard one can only handle 16. Their is a tutorial on altera wikis and is called Msi tutorial. To keep it short Msi expects a message format into the port and then sends the irq to the host. The host then reads the mask register in the cra and tells the irq initiator to desassert the irq. I'll look into the ip compiler to see what mechanisms they have. Some other specific ip cores have easier irq mechanics.

-Trukng