Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

PCIe Inbound Byte write data corruption ... SolutionID rd04172014_563

This describes the behavior I see ... solution id: rd04172014_563 last modified: may 02, 2014 product category: intellectual property product area: comm, interface & peripherals produc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Bob

Thank you for sharing information.

We conclude that the Txs 128-bit problem happens for 128-bit bus for both read and write.

AVMM bridge+HIP can handle the TLP correctly with 64-bits.