PCIe Inbound Byte write data corruption ... SolutionID rd04172014_563

Thanks Skbeh,

I got a reply per the SR I opened and Altera says there will be no Quartus based fix as indicated in the Knowledge Base information. This tells me the problem is in the Hard IP and the IP vendor didn't do a very good verification job.

I need to run Imbound byte writes and reads as part of a Cache Line stress test suite where the Host and EP share a Cache Lone but operate on different bytes .

For Flags and Status bytes , I can expand them to be DWORDS I believe ...

I am going to see if I can specify a 64 TXS Avalon MM slave port with Gen3 X 1 configuration as I know 64 bit TXS slave widths don't have the byte granularity issue.

Thanks, Bob.