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Altera_Forum's avatar
Altera_Forum
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16 years ago

PCIe HIP in SOPC simulation questions

I'm going through the training course PCI Express Hard IP Quick Start Guide with SOPC Builder to get a feel for the PCIe IP. I'm simulating the testbench that the PCI Express Compiler creates but I'...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

All I did was instantiate a PCIe component and ran the TB with no modification. It's weird that there should be any errors with this.

At least with the Avalon-ST variant I'm compiling it's only pulling in the stratixiv* libs (my target FPGA).

Have you tried commenting out the vlib/vmap/vlog statements associated with the other FPGA families it's pulling in, in the .do file? In my .do file, these statements are conditional on stratixiv_hssi_atoms.v existing in the build.

Peter