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andrecap's avatar
andrecap
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5 years ago

PCIe Hard IP Cyclone 10 peer to peer communication

Hi, we are trying to achieve communication between two endpoint FPGAs. The architecture of the system is as follows: PC (root complex) ...
BoonT_Intel's avatar
BoonT_Intel
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5 years ago

Hi Andrea,

I check with our Intel PCIe team, we acknowledge that the p2p that you want to achieve is called the ACS (Access control services). I am sorry to say that the PCIe IP in the FPGA is unable to support this. Any transaction of the FPGA must go to the root complex directly. As you can see none of the Intel FPGA document did mention about the p2p, the IP is not designed to achieve this type of transaction. The AVMM DMA IP is just to transfer the data to other function component under the same Physical link like DDR4 within the same FPGA.

Anyway, my previous feedback is still valid, to achieve p2p, it is also depending on the Root complex can support it or not.


andrecap's avatar
andrecap
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5 years ago

Hi BoonT,

you're right, but I was probably expecting this to be explicitly specified in the documentation...

Anyway, may I ask which part of the IP is lacking support?

Is there a way I can workaround this problem (for example: adjusting the TLP packet by "hand")?

The perspective of rewriting the whole driver isn't very appealing, so I'd like to know if there are other ways to solve the problem.

Thanks.

Kind Regards,

Andrea