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JKoty's avatar
JKoty
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5 years ago

PCIe Hard IP Cyclone 10 GX is not Detect in PC

Hi, we own DK-DEV-10CX220-A Cyclone 10GX DevKit. we are using Quartus Prime Version 18.1.0 Build 222 09/21/2018 SJ Pro Edition. We are implementing Hard PCIe IP (18.1, altera_pcie_a10_hip, Intel Ar...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Jan,

The above problem is occured due to , you did not configure the PCIe IP correctly . May be the PCIe is in reset state.

Can you please provide the LTSSM state signal tap for my reference.

  • JKoty's avatar
    JKoty
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi,

    I was able to scan status of basic signals some times after start. I am not sure how to trigger initial sequence for PCIe (If it is necessary for you) because Signaltap load image/ power cycle delay and so on... but for now it is looks like PCIe is stuck in state 03h - polling.compliance state

    This design is reference design :

    https://www.intel.com/content/www/us/en/programmable/documentation/ecx1522703736467.html, https://fpgacloud.intel.com/devstore/platform/2183/

    So pins and others project depend settings should be done correctly, but I can share with you some post build logs.

    Quartus only ask me for update IP core:

    But I do not thing that is really important for detecting PCIe in PC - what is my goal for now.

    Best Regards

    Jan