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jpang10's avatar
jpang10
Icon for New Contributor rankNew Contributor
5 years ago

PCIe hard IP Bringup on Cyclone 10 GX custom board

Hello, We are having trouble bringing up the PCIe Hard IP on our custom board. The hard IP is set up for gen 1 x1. It appears that coreclkout is stuck low and not toggling. Current setup: We ar...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Your design only has 1 lane, if this lane unable to lock, which means it can’t receive the TS1 and TS2 during the polling.active, and after 24ms timeout, it will return to the detect state, and NOT move to polling.configuration. Assuming the refclk is alright since both RP and EP are sharing the same clock source. If the rx_is_lockedtodata is toggling, it could be related to the board design where the incoming data has high BER or the board has introduced high jitter on the PCIe lane.


jpang10's avatar
jpang10
Icon for New Contributor rankNew Contributor
4 years ago

Thank you for all the help you provided, and helping me through the debugging process.

The problem was with my root complex PCB that I was testing with. After using a different board, everything works properly now.