New Contributor
Regular ContributorHi
This is glad to see there is good progress.
Questions:
1) After the fixed the clkusr pin, does the coreclkout work correctly with and without the following QSF setting?
set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_A10_DISABLE_RESET_CONNECTED_TO_CAL_BUSY=1
2) Does the PCIe refclk come from the gold finder? Or it is using a separate clock from your board?
3) What happens if you reboot the Host server after the program of the FPGA? Does the LTSSM behave the same?
Regards -SK
New ContributorAnswers to your questions:
1) After the fixed the clkusr pin, does the coreclkout work correctly with and without the following QSF setting?
set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_A10_DISABLE_RESET_CONNECTED_TO_CAL_BUSY=1
I no longer need this setting. I removed this from my qsf file and coreclkout_hip still functions properly (verified with counter), and I can also use coreclkout_hip as my sampling clock now.
2) Does the PCIe refclk come from the gold finder? Or it is using a separate clock from your board?
Yes, the PCIe refclk comes from the gold fingers.
3) What happens if you reboot the Host server after the program of the FPGA? Does the LTSSM behave the same?
Rebooting the root complex after programming the FPGA doesn't change the result. The LTSSM still behaves the same way. It toggles between state 0 (Detect.Quiet), 1 (Detect.Active), 2 (Polling.Active)
Something I noticed on the signaltap:
rx_is_lockedtodata and rx_is_lockedtoref are both toggling
Does this mean that the receiver isn't seeing data?
