New Contributor
Regular ContributorCan you attach a simplified PCIe design that can replicate the problem here? I would like to do a sanity check on your design. Thanks.
New ContributorThis project is based on https://fpgacloud.intel.com/devstore/platform/18.0.0/Pro/cyclone-10-gx-pcie-gen1-x1-avl-st/
I added a separate fpll to the project and that is working (using a counter in signaltap). However, the coreclkout_hip is still stuck low (also have a counter).
Debug1-4 are just LEDs on the board.
Please let me know if you see any problems. Thank you!
New ContributorWe have a separate question, is there a way to set up the hard IP to do a simple loopback? Can we simply connect the tx_st and rx_st together?
I see a lot of examples with the Example Application included in the platform designer.
We currently want to test if we can complete lane training with our root complex, but the coreclkout_hip staying low could be one of our problems.
Regular ContributorHi,
No, PCIe IP can't do a loopback test. What you can do is to using the Native PHY IP to achieve that.
I attached two SOF files, could you please capture the signal tap for each SOF, and send it back to me? I would like to see if there is any abnormality.
