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jpang10
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5 years ago

PCIe hard IP Bringup on Cyclone 10 GX custom board

Hello, We are having trouble bringing up the PCIe Hard IP on our custom board. The hard IP is set up for gen 1 x1. It appears that coreclkout is stuck low and not toggling. Current setup: We ar...
jpang10's avatar
jpang10
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5 years ago

Hi SK,

I've tried all 4 locations (1CT, 1CB, 1DT, and 1DB) of fpll, and verified that they were placed in the specified location using the chip planner after compiling. FPLL still doesn't output in any of the location, while IOPLL does.

I have a total of 3 boards, and have tried on 2 of them, and they behave the same way. IOPLL works, and FPLL doesn't.

I really appreciate all the help so far. Do you have other suggestions of what I can look into?

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jpang10
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5 years ago

Hi SK,

My FPLL works after I disabled calibration using
set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_A10_DISABLE_RESET_CONNECTED_TO_CAL_BUSY=1"

Would there be an issue if calibration is disabled? It appears that calibration was busy, holding my fpll in reset.

What could be some possible causes that calibration wasn't able to complete?