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jpang10's avatar
jpang10
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5 years ago

PCIe hard IP Bringup on Cyclone 10 GX custom board

Hello, We are having trouble bringing up the PCIe Hard IP on our custom board. The hard IP is set up for gen 1 x1. It appears that coreclkout is stuck low and not toggling. Current setup: We ar...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

In order to ensure we are aligned, I created a simple fPLL design, please find it in the attachment.

I verified this design in A10 GX setup, what you need to do is to change the device to C10 GX, pcie refclock pin, and maybe upgrade the fpll. This design is working fine on my side by checking from the signal tap.

  • jpang10's avatar
    jpang10
    Icon for New Contributor rankNew Contributor
    5 years ago

    I tried using your project as is, using Quartus Pro 20.1 and 20.4, with just upgrading the IP, and assigning the input clock pin assignment.

    pll_cal_busy = 1

    pll_locked = 0

    counter = 0183h (not changing)

    In addition to trying your project, I added a iopll and a 2nd counter for the iopll output. The iopll is working, with iopll_locked = 1 and counter2 incrementing.

    I also uploaded 2 projects. One using the project you uploaded in the previous message with just an upgraded fpll, and pin assignment. The 2nd one is with an additional iopll in the project, which is used to generate the pictures above.

    Thank you!