New Contributor
Regular ContributorThe pll_powerdown signal is high when you wanted to reset the PLL. You may do a reset after power on, for example, hold the fPLL at reset for some time, and then release the reset. Below is the example code you can use, where the clk_lock signal can connect to pll_powerdown.
reg [9:0] count_rst =0;
assign clk_lock = count_rst[9];
always @(posedge clk_100MHz) begin
if (count_rst[9]!= 1)
count_rst = count_rst +1;
else
count_rst = count_rst;
end
Besides, please try to use the IOPLL Intel FPGA IP and see if you also encounter the same problem.
Here is the Cyclone 10 GX Pin connection guideline, please review your custom board to ensure it meets the requirement:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-10/pcg-01022.pdf
New ContributorHi SK,
Here's the results from some of the recommendations to try:
I've tried holding the PLL pins in reset for longer period of time after power up, but that didn't make any difference to the results.
Using REFCLK_GXB (100MHz) as source:
IOPLL works: PLL locks, counter runs, and can be measured with oscope
fPLL doesn't lock, counter stays at 0
Using regular clk pin (50MHz) as source:
IOPLL works: PLL locks, counter runs, and can be measured with oscope
fPLL: not allowed
Using the output of IOPLL (100MHz) as source:
fPLL doesn't lock, counter stays at 0
I verified with the pin connection guide:
VCCR_GXB = VCCT_GXB = 0.95V
REFCLK_GXB : currently set as CML input, AC coupled with 0.1uF and 100 ohm termination
unused REFCLK_GXB : are tied to ground individually
CLKUSR : we have a free running 100MHz oscillator supply to that pin (in fitter report, Automatically reserve CLKUSR pin for calibration purposes is ON)
RREF_[T,B] : are individually tied to a 2kΩ resistor to gnd
Thank you so much for your help so far! Do you have other suggestions of what to look into or possible reasons why FPLL isn't functioning?
