New Contributor
Regular ContributorHi,
Most of the use cases of PCIe will share the reference clock with the host via the PCIe edge finger. Do you mean your design requires using a separate clock source between the Host and Endpoint? Besides, as per the C10 pin connection guidance, the DC coupling is allowed for PCIe reference clock if the IO standard is selected is HCSL. Please ensure you are using DC coupling as per requirement.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-10/pcg-01022.pdf
Does the pld_clk is connected with coreclkout_hip in your design? Next, you probably can create a simple design, and input the 100Mhz to an fPLL, and see if you can get the 62.5Mhz/125Mhz output.
New ContributorThanks SK!
Sorry for the confusion. The refclk does come from the golden fingers for the Cyclone 10GX, but is generated with CDCM9102 on the host side. This clock generator output is set to LVPECL, so we were following the datasheet to convert it to HCSL. We could also set the output to LVDS.
The pld_clk is connected to coreclkout_hip in the design.
For the simple project suggested:
I used the "fPLL Intel Arria 10/Cyclone 10 FPGA IP" selecting "CORE" for FPLL mode, and the pll isn't locking or outputting. The pll uses pcie_refclk (REFCLK_GXBL1C_CHBN) as input, and it's set to output 125MHz.
Could this explain why my coreclkout_hip was low and ltssm states aren't changing?
Just for some clarification, should pll_powerdown be 1 or 0 (I tried both and it still didn't work)? Does 1 mean the fpll is powered down and output = 0?
The signal tap uses the pcie_refclk as sampling clock and it appears to work since I can monitor other signals.
I plan to look into my input logic levels for the refclk, but if there are other suggestions of what to look into, please do let me know
