New Contributor
Regular ContributorYou may not see the "coreclkout_hip" switching as the sampling clock 100Mhz may be running slower. You can create a free-running counter in your design and clock by "coreclkout_hip" if the counter keeps increasing, which means the coreclkout_hip is alive. When the serdes_pll_locked is asserted, you should see the "coreclkout_hip" is running at the expected frequency.
New ContributorHi SK,
We added a counter for coreclkout_hip, but the counter stayed at 0.
We signaltap these signals using pcie_refclk as the sampling clock:
pld_clk_inuse = 0
serdes_pll_locked = 1
pld_core_ready = 1
reset_status = 1
perstn = 1
npor = 1 (hard tied to 1)
ltssmstate = 0
We also tried setting a signaltap with sampling clock coreclkout_hip, but the signaltap status is "waiting for clock".
When we were watching the pcie trainings on youtube, the powerpoint said to set refclk input to CML or HCSL, but on the device datasheet, it doesn't provide the I/O standards specifications like it does for the other standards (LVDS, RSDS, LVPECL, etc). Would you know the IO standards (like Vcm, VID, etc) for CML and HCSL for Cyclone 10GX?
Since we use the CDCM9102 clock generator to create the pcie refclk, we followed figure 9 (interfacing between LVPECL and HCSL) of the datasheet for the input of the refclk. Do you see any issues with setting the pcie_refclk inputs as HCSL and following that figure to shift LVPECL to HCSL?
Do you have other suggestions that we can look into?
Thank you so much for your help
