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jpang10's avatar
jpang10
Icon for New Contributor rankNew Contributor
5 years ago

PCIe hard IP Bringup on Cyclone 10 GX custom board

Hello, We are having trouble bringing up the PCIe Hard IP on our custom board. The hard IP is set up for gen 1 x1. It appears that coreclkout is stuck low and not toggling. Current setup: We ar...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

The coreclkout is derived from the PCIe Refclk, below are the posibilities of this problem:


  1. How do you connect the npor signal? Please ensure this signal is asserted or you may just tie it as "1" in the design.
  2. You may try to use the PCIe refclk as the sampling clock in signal tap and check if the serdes_pll_locked signal can be asserted? If not, it could be something wrong with the refclk.


Regards -SK


  • jpang10's avatar
    jpang10
    Icon for New Contributor rankNew Contributor
    5 years ago

    Thank you for your reply, SK!

    1. npor is (user_input_nrst & perstn), from signal tap it shows that it goes high. I also tried tying it straight to 1'b1, but the lttsmstates shown on the root complex are still the same

    2. I used the PCIe refclk as the sampling clock, and do see serdes_pll_locked goes high. I also added the coreclkout to the signaltap, but doesn't see it switching.


    Do you have any suggestions on what else we can look at?

    Thanks!