PCIe Hard IP - Can 'valid' De-assert Between SOP and EOP During DMA Read Completion?

Hi Wincent_Altera​ ,

Sorry for the delayed response.

Regarding your previous comment, I understand that this might be a slightly grey area. It would be really helpful if you could point me to any available documentation or references that clarify whether the PCIe Hard IP guarantees continuous valid assertion from SOP to EOP for a given TLP.

I’ve observed this behavior in my simulations, and I just want to make sure I’m aligning correctly with the intended behavior of the Hard IP. Without confirmation on this, I’m unsure whether to treat this as a BFM limitation or if the DUT should be updated to handle such scenarios.

Any guidance or pointers would be greatly appreciated, as this will help me proceed in the right direction.

Regards

Abhi Krishnan R