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Altera_Forum
Honored Contributor
Honored ContributorPCIe Gen3 on DE5-net/Stratix V board
Hi All, I've been trying to create a simple design using the Stratix V PCIe 3.0 x8 core with an Avalon-ST interface. I can compile my design, and load it onto the FPGA, but link training fails...
Altera_ForumHonored Contributor
Honored ContributorHi David,
Pinning the slot to Gen3 seems to have fixed the problem, thanks! For reference, my analog settings above match the ones in the example design online. Mu
