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Altera_Forum's avatar
Altera_Forum
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16 years ago

PCIe freezing

Hi, I have strange problem with PCIe IP. I have a custom board with ArriaGX and PCIe instantiated using MegaCore flow with AvalonST interface. The PCIe works (there are some DMAs running, targe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

PH/PD changing while receiving write requests is expected, and they do recover. NPH looks good as well. NPD=0 looks bad but might be correct as it’s useless to allocate memory for non-posted data when a native Endpoint does not support non-posted traffic with data. At least I think it doesn’t.

About CPLH/CPLD: Amazing they are zero. Maybe they get positive once non-posted request are issued by the IP.