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Altera_Forum
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11 years ago

PCIe Force Gen1 Link

I've built a design around a Stratix V and the Avalon-ST Hard IP Core. The device is designed for Gen3x8 which is working fine. I now want to connect the design to a laptop via a Gen1x1 Express...
Altera_Forum's avatar
Altera_Forum
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11 years ago

The hard IP reconfiguration interface is use to dynamically modify the value of configuration registers that are read-only at run time, such as device ID and vendor ID. But even this also very rare users use it.

The speed and lanes width were already setup and pre-defined during enumeration and handshaking process between rootport and endpoint.

I'm not sure if the reconfiguration interface can be used to modify the speed and lane width.