Forum Discussion
Occasional ContributorPCIE example issues
Hi Pieter,
And yes, indeed, if you run the software test as in figure 12, then the application accepts traffic loadup to MAX.PAYLOAD. BUT NOT THE TESTBENCH / APPS in simulation!
Yes. As in my previous reply, the testbench provides simple method to do basic testing and this does not cover all the traffic profile stimuli. If user wants to simulate with what is not covered in the testbench, user has to modify the testbench based on their requirements.
So, i think i am on the edge of improving the testbench and APPS to payload = max.payload. My question: if i would share this code with you, would INTEL be willing to compensate me for this effort ? (i think INTEL does not deliver what it says it does as described in the manual)
I apologize for the miscommunication if there is any. The reason I asked if you are willing to share the modification earlier is because there are some hobbyists share information, what they have created or method to solve problems in this public forum. Please do not share if the content is confidential or non-public accessible.
Thanks for your understanding. Do let me know if you have any questions or concerns.
Best regards,
KhaiY
Regular ContributorHi Pieter,
I am sorry for the delay in response. Thank you for your patience.
I discussed with the team, the testbench does not have the flexibility and does not cover certain traffic profile stimuli. It would be a time consuming process to edit and debug. Is there any ultimate goal that you would like to achieve from this?
Thanks
Best regards,
KhaiY
- PVanL
Hi KhaiY,
thanks for response, but i don't understand it.I thought i explained my goals (see earlier posts):
What i really want, is connect my ethernet PHY, via the INTEL Low Latency MAC, to the PCIE Hard IP (gen2 x 4) and map it onto the cyclone10GX development board.
(I have in the INTEL design example for Low Latency MAC, replaced the INTEL PHY iwth my own PHY, and it runs in simulation, and i still have some difficulties in getting the tranceiver properly mapped onto the cyclone10GX).
If you do have an example with this, (but then of course with the INTEL PHY), that would be most welcome!For PCIE testbench I am using the example of UG-01145_avst. The difficulty is not in the testbench, but in the APPS component, in fact, i believe it is in the TLP parser that is not built to send anything back but ONE DWORD of 4 byte. I tried to modify the TLP parser to make it suitable for 2 DWORD of data, but somehow the Hard_IP PCIE block makes a mess out of it.
The UG-01145 document says (page 157): "It can only handle received read requests that are less than or equal to the currently set Maximum payload size option specified under PCI Express/PCI
Capabilities heading under the Device tab using the parameter editor. Many systems are capable of handling larger read requests that are then returned in multiple completions.
That would be good enough for me, but i dont get it working! It only seems to work for 4 Bytes!
And if you look at the code, (driver_downstream.v), line 270 - 289, the length is cut off at 4 Bytes, and there is a remark:
line 271: //TODO extend to more than 1 DW.So, it seems as there is some work to be done ??????!!!!!
So, you can help me in several ways:1/ provide me with a TLP parser that is able to reply correctly with packets of many bytes. I think i can manage to integrate that into the APPS entity and the MEM entity, and modify the testbench such, that it maybe does not compare, but at least i can verify manually that received = send
OR:
2/ provide me with an example where your LL_MAC_10GBASE_R example is already integrated into a PCIE gen2x4 example
OR
3/ explain me how, without using the testbench, but by directly building the above (PCIE + LLMAC_10GBASER) and synthesise/place/route it onto the Cyclone10GX development board, and run a software test similar to the one described in AN 855: PCI Express* High Performance Reference Design for Intel® Cyclone® 10 GX.
Thanks for your feedback!
regards, Pieter
