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SLabe's avatar
SLabe
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7 years ago

PCIe Example Design Simulation Failing

Unsing Quartus 18.1 Pro. Generated Gen2x1 or Gen3x4. When compiling in modelsim, I get the following: # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Star...
SLabe's avatar
SLabe
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Hi Andy, yes Windows. I was actually careful of that and generated the example design at the C:/ level.

Also, there is a pkg file generated at the same depth... so should not be an issue. An Intel FAE colleague also reported that he had observed the same issue...

Thanks,

  • User1589943631307909's avatar
    User1589943631307909
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi， SLabe，I got the same simulatioan error and indeed could not generate the simulation file named "pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq.sv" . OS of my computer is Win10 , version of Quartus Prime Pro Eniton is 18.1 and simulation tool is Questa Sim-64 10.6c. I got error messages as follows, do you know how to fix it now? Thank you very much.

    # vlog -reportprogress 300 -sv ../../../ip/pcie_example_design_tb/pcie_example_design_inst_board_pins_bfm_ip/altera_conduit_bfm_181/sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq.sv -L altera_common_sv_packages -work altera_conduit_bfm_181
    # ** Error: (vlog-7) Failed to open design unit file "../../../ip/pcie_example_design_tb/pcie_example_design_inst_board_pins_bfm_ip/altera_conduit_bfm_181/sim/pcie_example_design_inst_board_pins_bfm_ip_altera_conduit_bfm_181_o4cgbkq.sv" in read mode.