SLabeOccasional Contributor7 years agoPCIe Example Design Simulation Failing Unsing Quartus 18.1 Pro. Generated Gen2x1 or Gen3x4. When compiling in modelsim, I get the following: # Model Technology ModelSim - Intel FPGA Edition vlog 10.6d Compiler 2018.02 Feb 24 2018 # Star...Show More
Recent DiscussionsStratix 10 fPLL is cascade source mode doesn't lockmipi csi2 tx, upper limit of video widthAgilex 5 SDI 148.5 and 148.35 MHz refclksAVST FIFO and AVST Demultiplexer IP Simulation BehaviorSolvedSystem ID IP Timestamp Issue