PCIE example design - error compiling with Modelsim
I generated an example PCIE design for Arria 10. I then go to the sim/mentor directory, source the msim_setup.tcl and run ld, ld_debug or com TCL commands from Modelsim. In all cases, I get the following error:
-- Compiling module twentynm_xcvr_avmm
#
# Top level modules:
# twentynm_xcvr_avmm
# End time: 10:38:42 on Jul 30,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.6c Compiler 2017.07 Jul 26 2017
# Start time: 10:38:42 on Jul 30,2018
# vlog -reportprogress 300 -sv ./../../altera_xcvr_atx_pll_a10_180/sim/mentor/twentynm_xcvr_avmm.sv -L altera_common_sv_packages -work pcie_example_design_altera_xcvr_atx_pll_a10_180
# ** Fatal: Unexpected signal: 11.
# ** Error: ./../../altera_xcvr_atx_pll_a10_180/sim/mentor/twentynm_xcvr_avmm.sv(38): in protected region
I tried this with Quartus 16, 17 and 18, with similar results. Given that the file is encrypted, I am at a loss of how to debug this further. Please help.