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Altera_Forum
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16 years ago

PCIe core MSI-X support

I have added MSI-X support to an implementation of the Altera PCIe core we're already testing in the lab. My understanding, is that with MSI-X enabled in the megawizard and my vector table offset se...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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Yes, either the first one (if addr mod 8 == 4) or the second one (if addr mod 8 == 0).

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I made in this way... but problem was that in 2clk packet I send

Clk2: PCIe_data_out [63:0]<= {msix_Msg_Lower_Addr[msix_Number], Sig_Packet_Data_field [31:0]}

but should be

Clk2: PCIe_data_out [63:0]<= {Sig_Packet_Data_field [31:0],msix_Msg_Lower_Addr[msix_Number]}

Thank You for help!!!! :)

Now everything is ok.

P.S. 1st PC understand write packet with 64 bit addr even if upper addr is all 0... but other don't understand... (they understand just 32bit addr packets)