PCIe core MSI-X support

Do You mean 3-DWord Header TLP and memory write request 32bit addr?

So how should packet look like if msix_Msg_Upper_Addr[msix_Number] is all zeroes?

Like this - only two clk:

assign Sig_Packet_Type_field = 8'h40; // 32bit addr

assign Sig_Packet_Length_field = 10'b00_0000_0001; // 1 DWORD

// LastBE = 4'h0, FirstBE = 4'hF

Clk1: PCIe_data_out [63:0]<= {Requester_ID, 16'h00_0f, Sig_Packet_Type_field, 14'b0, Sig_Packet_Length_field};

Clk2: PCIe_data_out [63:0]<= {msix_Msg_Lower_Addr[msix_Number], Sig_Packet_Data_field [31:0]}

Or like this – 3 clk:

assign Sig_Packet_Type_field = 8'h40; // 32bit addr

assign Sig_Packet_Length_field = 10'b00_0000_0001; // 1 DWORD

// LastBE = 4'h0, FirstBE = 4'hF

Clk1: PCIe_data_out [63:0]<= {Requester_ID, 16'h00_0f, Sig_Packet_Type_field, 14'b0, Sig_Packet_Length_field};

Clk2: PCIe_data_out [63:0]<= {msix_Msg_Lower_Addr[msix_Number],32'b0}

Clk3: PCIe_data_out [63:0]<= {Sig_Packet_Data_field, 32'b0};

It seems to me that I tried already both variants but they don't work :( HELP! :)

P.S. I checked msix_Msg_Upper_Addr is all 0!

On 1st PC where MSI-X are working, I send 4DW header and msix_Msg_Upper_Addr still is all 0...