PCIe core MSI-X support

Thank for all.

Now my MSI-X table for two entry looks line:

msix0_addr = msix1_addr = FFFFFFFFFFF0F00F // I test it on 64 bit Linux.

msix0_ctrl = msix1_ctrl = FFFFFFFE // LSB is 0, all ok.

msix0_data = FFFFFFA1

msix1_data = FFFFFFA9

looks good too.

I'm get msixcsr data from tl_cfg bus.

cfg_msixcsr[15] - MSI-X Enable – good.

cfg_msixcsr[14] - 0, “each vector’s Mask bit determines whether the

vector is masked or not. and msi_ctrl[0] i have 0.” Yes. I have.

I'm make memory write.

TLP_FMT_4DW_W, TLP_TYPE_WRITE, Last BE = 4'b0000, First BE = 4'b1111.

Adress is FFFFFFFFFFF0F00F.

But no interrupt.

looks very strange LSB in FFFFFFFFFFF0F00F. It's must be 2'b00.