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No, it’s not within specs of the PCIe hard IP core AST interface to send with gaps if the hard IP doesn’t ask for a gap. Look at the signal description of tx_st_valid int the PCI Express Compiler User Guide (quote is from v10.0):
So, as long as the hard IP doesn’t do flow control by deasserting tx_st_ready<n>, you absolutely have to provide data until the end of the TLP packet.
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Wow, thanks, I totally missed that in the specs. Guess now I know why they make that a requirement. :) Wish their core had some sort of warning for violations of this rule.
Luckily, my real logic has no trouble with the no-stalls requirement, once I remove my fake-stall-inserter. This does make it considerably harder to verify that customer application logic will properly handle IP-generated stalls on this interface, but at this point I guess I've tested my code pretty well.
Thanks for the clarification.
-Brett
Honored Contributor
