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Altera_Forum
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14 years ago

PCIe core gets confused with stalls. Help?

I have a Stratix IV GX design up and running using the PCI Express hard core. In runs in simulation and in HW. I'm using PCIe gen 1 x4. My simulation environment borrows heavily from the chained D...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

No, it’s not within specs of the PCIe hard IP core AST interface to send with gaps if the hard IP doesn’t ask for a gap. Look at the signal description of tx_st_valid int the PCI Express Compiler User Guide (quote is from v10.0):

--- Quote Start ---

tx_st_valid<n>:

Clocks tx_st_data<n> into the core. Between tx_st_sop<n> and tx_st_eop<n>, must be asserted if tx_st_ready<n> is asserted.[…]

--- Quote End ---

So, as long as the hard IP doesn’t do flow control by deasserting tx_st_ready<n>, you absolutely have to provide data until the end of the TLP packet.