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Altera_Forum
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15 years ago

PCIe Compiler 10.1 Soft Core can't meet timing?

Good evening, I'm trying to use the PCIe Soft IP Core in a Cyclone IV E design, but I can't seem to get the chaining_dma example project to meet timing. I'm using a PX1011B PHY (setting the co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

With the help of some more experienced friends it appears that the trouble was due to a few things:

1) the "Placement Effort Multiplier" in the Advanced Settings of the Fitter is now set to 4.0 (default value was 1.0).

2) the Optimization Technique in the Analysis and Synthesis Settings is now set to "Speed"

With these two changes I did NOT need to set anything different under the physical synthesis settings (the user guide suggests setting "Perform register retiming", "Perform register duplication" and "Perform physical synthesis for combinatorial logic." Setting these things does not allow the core to meet timing; I had to set the two things listed above in order to meet timing.

One thing that I noticed did NOT matter was the PHY interface clock speed; 250MHz IO does not appear to be a problem with the I8L part.