PCIE CHANGE SPEED

Question

Good morning, I've a design pcie For Arria 10 based on the IP PCIE SRV-IO gen3 x8. I would like to reconfigure the link speed to 5.0g after FPGA configuration. After some research, I've found the reg specification for hip_reconfig interface on the arria 10 pcie core. After booting we proceed with the access to this register us your timming specification on image : "Figure 6.6 Hard IP Reconfiguration Bus Timing of Read-Only Registers"of Arria 10 Avalon-MM Interface document paraph Hard IP Reconfiguration Interface.After accesing to register, we read the content from address 0x8 and ahead instead from 0x89.
0x89 15:0 Vendor ID. 0x11720x8A 15:0 Device ID. 0x00017:00x8B Revision ID. 0x010x8C 15:0 Class code[23:8]. —0x8D 15:0 Subsystem vendor ID. 0x11720x8E 15:0 Subsystem device ID. 0x00010x8F — Reserved. —0 Advanced Error Reporting. b'00x903:1 Low Priority VC (LPVC). b'0007:4 VC arbitration capabilities. b'0000115:8 Reject Snoop Transaction. b'00000000

We also write the register 0x00 to '0' for enable the writes on that memory area.
After write any value the BIOS cant find the new value. (Including reseting BIOS without FPGA reconfiguration, the value on the bus is correctly written and readed).This bus is doing nothing on the pcie enumeration, why??? Something missundertood. We need to do something with the (test_in signals??)
After some effords we find also an option on the core instanciation called: speed_change_hwtcl, and under the installation repository, appears to be the next files:
vlog "../../vhd/core_reconfiguration/altpcie_hip_eq_bypass_ph3.v" -work altera_pcie_a10_hip_180 vlog "../../vhd/core_reconfiguration/altpcie_sc_bitsync.v" -work altera_pcie_a10_hip_180 vlog "../../vhd/core_reconfiguration/altpcie_sc_dprio_rd_wr.v" -work altera_pcie_a10_hip_180 vlog "../../vhd/core_reconfiguration/altpcie_sc_dprio_seq.v" -work altera_pcie_a10_hip_180 vlog "../../vhd/core_reconfiguration/altpcie_sc_hip_vecsync2.v" -work altera_pcie_a10_hip_180 vlog "../../vhd/core_reconfiguration/altpcie_sc_lvlsync.v" -work altera_pcie_a10_hip_180 vlog "../../vhd/core_reconfiguration/altpcie_sc_lvlsync2.v" -work altera_pcie_a10_hip_180 vlog "../../vhd/core_reconfiguration/altpcie_sc_dprio_top.v" -work altera_pcie_a10_hip_180 vlog "../../vhd/core_reconfiguration/altpcie_sc_ctrl.v" -work altera_pcie_a10_hip_180
This core connects internally to the hip_reconfig_* interface, and also seams to we writting a new speed on the core but its done on an unspecified address d181???
localparam DPRIO_CTRL_REG_2_TLS = 10'h2;localparam DPRIO_CTRL_REG_111_CSEB = 10'd111;localparam DPRIO_CTRL_REG_181_EN_SPD_CHG = 10'd181;could you please provide a memory map for that register on the hard pcie ip?? Is posible to renegotiate the speed after device is configured?. Thanks in advance and best regard.

skbeh · Answer

The Hard IP reconfiguration interface only can be used to reconfigure the read-only register. For instance, use this interface to modify the device ID register at run time. It cannot be used to change the pcie link speed from Gen3 to Gen2.
Users need to set the intended link speed during IP parameterization, recompile Quartus to get the .sof, then reconfigure the device.

alega1 · Answer

Hello, we can't modify the deviceID either, could you provide some example? We just want to enumerate to the BIOS a maximun speed of gen2. We can do it from intel BIOS, but this option is not available for AMD processor, and we would like to change the value of maximun speed supported.

Thanks in advance and best regards.

skbeh · Answer

A10 user guide below at section '5.7.1. Hard IP Reconfiguration Interface' has the description and timing diagram of hip_reconfig_* interface.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf#page=56

skbeh · Answer

May I know what is your intention to modify the deviceID? Is that you want to try using the hip_reconfig* interface to modify the deviceID, after that use the same interface/method to also modify the speed_change_hwtcl to change the pcie link speed?

alega1 · Answer

Good morning, first of all, first of all,  the memory map is missed on the paper!!! "https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf#pag..." We have the signals description, but nothing about the addressing of that bus!!!!, or some information about the register to be read or write????. We have found an memory map on UG-01145_avmm, but the address doesnt fit with the data readed on the real core (we use Signal Tap to see all the content on the bus). The fisrt word vendor id is readed from address 0x08 intead form address 0x89!!! And so on (everything seem to be offset from address 0x89 to address 0x8???? how is that possible? Could you provide the internal memory map of the hard IP for pcie???). We just modify the device id to test the interface its workuing, but not working properly. The BIOS always read the original value, no the written througth the reconfiguration interface. We also tried to write the register 0x9F, we try to modify the PCie Capability Version from compliant PCIe Specification 3.0 to PCIe Specification 2.0, in order to force BIOS to enumerate our device as a gen2 compliance. On pcie standard there is register called Link Capabilities Register, for enumeration of supported bandwith and Link width, there is any chance to be mofied from that interface?? We attach our user code and also the UG-01145. Thanks in advance and best regards.

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PCIE CHANGE SPEED

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